Traditional semiconductor devices utilized planar devices in which portions of a substrate are doped to create a conductive region. This technology has been used in manufacturing ultra-large scale integrated (ULSI) circuits incorporating metal-oxide-semiconductor field effect transistors (MOSFETs). Reduction in the size of MOSFETs has provided continued improvement in speed, performance, circuit density, and cost per unit function over the past few decades. As the gate length of the conventional bulk MOSFET is reduced, the source and drain increasingly interact with the channel and gain influence on the channel potential. Consequently, a transistor with a short gate length suffers from problems related to the inability of the gate to substantially control the on and off states of the channel.
Phenomena such as reduced gate control associated with transistors with short channel lengths are termed short-channel effects. Increased body doping concentration, reduced gate oxide thickness, and ultra-shallow source/drain junctions are ways to suppress short-channel effects. However, for device scaling well into the sub-30 nm regime, approaches involving the use of three-dimensional devices, such as fin field-effect transistors (finFETs), are being investigated to improve the short channel effects. Generally, fins are produced by etching a silicon substrate to form the fins.
These three-dimensional devices have been found to greatly improve the operating characteristics of the semiconductor devices. However, the three-dimensional devices may require considerably more time designing and laying out the circuit due at least in part on the increase in active areas. A planar device typically has a single, large active area, whereas a finFET device may have multiple fins. Each fin must be defined on the layout, and may require a substantial increase in effort and expense to define.
Accordingly, there is a need for a method of designing a circuit layout having three-dimensional structures.